Modern and future electrical infrastructures will be characterized by an increase of real-time processes implemented in dedicated hardware, for example as real-time wide-area controllers. Real-time hardware-in-the-loop (HIL) simulation is an approach that allows the development of modern control systems for machines and converters, flexible AC transmission systems, high-voltage DC converters and more. A process-- in this case, a power plant-- is replaced by a digital numerical model of the device that, contrary to an offline simulation, has the capability of being solved in real-time, in our case, by using an FPGA. The goal is to numerically solve the system of differential equations that govern the system in a discrete amount of time.

Modified nodal analysis or MNA is a methodology that applies to electrical grids and networks. It is based on the so-called nodal admittance matrix formulation, where essentially each branch of the electrical system is replaced by its numerical discretization and solved.

The second point of our solver is that it’s able to integrative passive elements, namely RLC lamp devices, together with transmission lines, namely devices where propagation takes place, namely the states of the two boundaries of the elements are solved by means of an algebraic equation.

The third element that we have implemented in the solver is the so-called fixed admittance matrix nodal method. That allows us to replace the switches by means of the equivalent circuitry that you see on the bottom right hand of the slide. So why is this method very important? Because each time we have a change of a switch status, there is a change of the admittance matrix of our system and this requires a refactorization of this matrix that normally takes time; it takes a time window which is much larger than the typical integration time-steps that are required by these types of real-time simulators, and the fixed admittance nodal method fixes this type of problem.

We have deployed our solver by using the CompactRIO platform of National Instruments and in particular we have used a 9118 FPGA chassis, which is composed by Xilinx Virtex 5 LX 110 FPGA. In this FPGA chassis we have interconnected some analog input and outputs, typically characterized by a 16-bit sampling and a sampling frequency of 1 megahertz for the analog inputs and 100 kilohertz for the analog problems.

The solver has been fully implemented by using the LabVIEW FPGA programming environment by using specific blocks for the solution of and the speedup of the more computationally intense part of the solver. The FPGA solver performs the solution of the nodal analysis, taking into account the inputs and the outputs coming from the I/O models.

So the computational time is on the order of 1 microsecond and it is worth noting that the largest part of this computational time is taken by the converted analog-to-digital converter, which is assembling everything at 1 megahertz so that the computational time, which has taken awhile to solve the analysis, is on the order of 100 nanoseconds.

Comparison with offline simulations showed a very good match. We’re taking into account a transmission line where a phase to ground unsymmetrical fault is occurring. The line is 30 kilometers long. And we are computing the results of the simulator by using an offline simulation done by one of the popular tools used in this field, which is the EMTP.

We have developed a general-purpose electrical system FPGA-based real-time simulator which has been turned into an FPGA in the National Instruments CompactRIO system. The development FPGA real-time simulator integrates several tools which are the fixed admittance matrix nodal method, the transmission line treatment, together with the modified nodal analysis. The parallelization of the implemented algorithm to solve the MNA equation has been implemented and this has allowed it to reach low integration time steps in the order of microseconds. Comparison with offline simulations showed a very good match with very good computational efficiency.

PRESENTER: Dr. Mario Paolone
Dr. Paolone received his EE M.Sc. and Ph.D. from the University of Bologna, Italy. In 2010, he received Associate Professor eligibility from the Politecnico di Milano, Italy. Currently, he is Associate Professor at the Swiss Federal Institute of Technology, Lausanne, Switzerland, where he is chairing the Distributed Electrical Systems Laboratory.


IEEE Spectrum: Real-Time HIL Simulation of Grid-Tied Switched-Mode Power Systems

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