Simon Deleonibus 2011-2012 Seminar Series
December 2, 2011
Nanoelectronics linear scaling appeals to new 3D integration schemes in order to continue Moore’s law. Unique opportunities exist to increase the device's performance, system complexity and also to reduce power consumption of mobile handheld objects. New design and functional architecture will be possible by mixing logic and memory devices to save power consumption and introduce new applications by using neuromorphic or bio inspired approaches. Devices other than CMOS can be co-integrated with CMOS to interface the outside Multiphysics world (MEMS, sensors and actuators, RF devices, power devices,etc.) allowing new functionalities. 3D Wafer Level Packaging and System on a Wafer allow these new routes.