Presented at DVCon U.S. 2021
Presented by members of the SystemC Verification Working Group, this workshop introduces the basic concepts of UVM-SystemC and shows how constrained randomization and functional coverage can be integrated to build a verification environment using the current UVM-SystemC library. Currently, the working group is working on the standardization of a common randomization layer based on CRAVE, a C++ and SystemC constraint randomization library. The workshop will show how constrained randomization can be used within SystemC and integrated into UVM-SystemC verification environments.
Thilo Voertler, COSEDA Technologies GmbH
Dragos Dospinescu, AMIQ
Martin Barnasconi, NXP Semiconductors
Stephan Gerth, Bosch Sensortec GmbH