SystemC Evolution Fika - Part 5
April 7, 2022
We briefly review the major obstacles that stand in the way of standard-compliant parallel SystemC simulation and then present the Recoding Infrastructure for SystemC (RISC), which is a compiler-based approach to overcome these obstacles. RISC enables the parallel simulation of unmodified SystemC models with maximum standard compliance. Reference: R. Dömer: "Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation", IEEE Embedded Systems Letters, vol. 8, no. 4, pp. 81-84, December 2016.
Presenter: Rainer Dömer | University of California, Irvine, CA, USA
Part 6:
vimeo.com/699687856
For more information:
systemc.org/events/scef202204/
