Keynote: Verification Challenges, Trends and their Practical Adoption -- An ASIC Manager’s Perspective

Speaker: Madhav Rao, SVP VLSI BU, Tessolve Semiconductor Pvt. Ltd.

Presented at DVCon India 2022
September 6, 2022

Multiple surveys suggest that verification continues to take a larger percentage of ASIC pre-silicon development effort and time (typically 60 – 70%) and companies continue to adopt newer methodologies and technologies to increase productivity, quality and time-to-market. However, there are barriers to adoption of such technologies. From the perspective of an engineering manager, new verification techniques should reduce effort and budget whilst improving project schedule, productivity and design quality to help ensure first-pass silicon success. However, it is not always clear which techniques will achieve these for their specific products and development flows and once selected how they can be seamlessly incorporated into existing flows where their benefits can be realised and, ideally, measured. This talk will look at a range of verification techniques and improvements and provide suggestions on how they can be assessed, selected and adopted to make a positive contribution to key project metrics.