DVCon U.S.

  1. Opening session and welcome of DVCon U.S. 2022

    Presented by Vanessa Cooper, DVCon U.S. 2022 General Chair

    # vimeo.com/720261109 Uploaded 8 Views 0 Comments
  2. Workshop presented at DVCon U.S. 2022

    Presented by Siemens EDA

    By: Russell Klein, Siemens EDA

    MatchLib is a SystemC based throughput accurate communication package developed by Nvidia and available as open-source. It can be used to model common buses like AXI. It enables much faster simulation of a design while retaining throughput accuracy. At some point in the design cycle one or more processors will be included in the design,
    along with software. This workshop will describe how to bring a processor into a MatchLib design in 3 forms: host code execution, fast processor model, and RTL. We will walk though examples using the RISC-V Rocket core, a MatchLib modeled interconnect, and a simple inferencing application. The inferencing application will be run in simulations both as an abstract model in SystemC and as RTL. We will use High-Level Synthesis to create the RTL from the SystemC implementation. This workshop will show the example design running at different levels of abstraction, exploring the different verification objectives that can be achieve at each stage of the design process.

    # vimeo.com/720270549 Uploaded 15 Views 0 Comments
  3. Session presented at DVCon U.S. 2022

    Session Chair: Dave Rich

    This session consists of 4 presentations.

    1) Caching Tool Run Results in Large-Scale RTL Development Projects

    By Ashfaq Khan, Intel Corporation

    2) Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed System

    By Jin Choi, Samsung Electronics Co., Ltd.; Sangwoo Noh, Samsung Electronics Co., Ltd.; Sooncheol Hong, Samsung Electronics Co., Ltd.; Hanna Jang, Samsung Electronics Co., Ltd.; Seonhee Yim, Samsung Electronics Co., Ltd.; Seonil Brian Choi, Samsung Electronics Co., Ltd.

    3) Machine Learning Based Verification Planning Methodology Using Design and Verification Data

    By Hanna Jang, Samsung; Seonghee Yim, Samsung; Sunchang Choi, Samsung; Seonil Brian Choi, Samsung

    4) Optimizing Turnaround Times In Continuous Integration Using Scheduler Implementation

    By Robert Strong, Samsung

    # vimeo.com/720267416 Uploaded 8 Views 0 Comments
  4. Tutorial presented at DVCon U.S. 2022

    Presented by members of Accellera System Initiative

    By: Tom Fitzpatrick, Siemens EDA; Matan Vax, Cadence Design Systems; Adnan Hamid,
    Breker Verification Systems; Hillel Miller, Synopsys, Inc.

    The tutorial will highlight the power and flexibility of the Portable Stimulus Standard from Accellera by walking through several real-world examples. Beginning with a brief overview of the standard, we will show how to use PSS to model stimulus for a variety of applications, from which multiple target-specific test implementations may be generated.

    # vimeo.com/720254905 Uploaded 11 Views 0 Comments
  5. Workshop presented at DVCon U.S. 2022

    Presented by Verilab

    By: Jeff McNeal, Verilab, Inc.; Jeff Vance, Verilab, Inc.; Paul Marriott, Verilab, Inc.

    Workshop Motivation
    We have found over the years that design projects face unnecessary risks and inefficiencies due to insufficient or ineffective verification planning. A poor (or missing) plan does not allow the team to easily track actual progress towards the planned schedule. On many projects, verification plans are often written early in the project, and then completely ignored by the team, never getting updated or revised as the project changes and progresses. Additionally, it is rare to find training on how to do verification planning, resulting in ad-hoc approaches. The following consequences are typically seen as a result:

    • There is ambiguity on the verification status throughout the project. The team is unable to accurately articulate where the project is in the development cycle, which can cause mistrust from management.

    • Tasks are given inappropriate priority, often block-based instead of feature-based.

    • There is poor communication within the team. Without clearly defined deliverables and schedules from the verification team, the rest of the project members can’t plan their work.

    • There is a lack of risk management for common surprises, such as requirements changes, unclear specifications, blocking bugs, and implementation challenges.

    Ultimately, these problems will reduce design quality, result in missed milestones, and generally make everyone’s lives unnecessarily stressful.

    Workshop Content
    In this lecture-style workshop, we will address some common problems we have seen faced by verification teams, and provide techniques and guidelines based on extensive project experience. Attendees will learn how to identify common pitfalls that can doom a verification plan, and how to avoid them. These include the following:

    • Focus on Features: We will demonstrate techniques for feature identification that allow us to be more strategic and accurate in our planning. These techniques produce better plans than the common approach of merely dividing a design by RTL blocks. We show how to break features into smaller sizes for more accurate scheduling, define agile- based user stories, and apply Mutually Exclusive, Collectively Exhaustive (MECE)

    • Linear Progress: Attendees will learn how to divide work based on incremental sections, building on what is already completed. By verifying smaller sets of features, we can break away from the restrictions of block-based testbench features that limit our progress.

    • Actionable Definitions of Done: Defining deliverables in terms of what will be demonstrated provides more clarity and accuracy over the lax definitions of done that are commonly used. It reduces the chance of work falling through the cracks and ensures the team is in alignment from the beginning. Attendees will learn how to craft
    deliverables that clearly communicate what feature is being verified without ambiguity from project changes.

    • Modern Methodology: New standards and larger chip sizes mean greater reuse than ever, both of the RTL components as well as the testbench. Modern verification means that it is necessary to address items such as UPF, PSS, emulation, as well as requirements tracing in addition to the traditional tasks like scheduling and coverage planning.

    • Efficiency: Our techniques help to simplify and compartmentalize verification plans. This can assist in getting work started sooner, as well as avoid documentation rot and allow the verification team to be more responsive to changes during the project.

    By combining these techniques teams will be able to plan more efficiently, begin verification more quickly, and progress more steadily. They will also be better able to communicate their progress and status with the rest of the development team. The techniques we will be teaching are compatible with, but do not depend on, agile development, UVM/SV, or any particular vendor’s tools. The techniques will touch on how to plan the development of various blocks of the testbench in a UVM style testbench, including TB infrastructure, sequences, coverage and checking.

    # vimeo.com/720269925 Uploaded 21 Views 0 Comments

DVCon U.S.

Accellera Systems Initiative

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical…

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The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.


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