1. INTEL - James Reinders - “Parallel Programming for C and C++ done right”


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    I Multicore World, 27-28 March 2012, Wellington, New Zealand Abstract - Parallel Programming is Programming. But our favorite languages, including C and C++, were not designed with this in mind. Intel has been very aggressive in support of solutions, including open sourcing substantial implementations to help. This includes creating the most popular parallel model for C++, Intel Threading Building Blocks (TBB), and the creation of the Cilk Plus open standard and helping create multiple compiler implementations to support Cilk Plus. Cilk Plus may be the way to extend C and C++ in languages, to complement the highly portable C++ template library TBB. Intel believed in this enough to acquire the technology from Cilk Plus, invest to bring to market, and then open sourcing of all the key elements to pave the way for wide adoption. In this talk, James will make his case for why Intel has done this by examining trends in software and hardware. James will also explain how to participate in evolving Cilk Plus to meet all our needs. BIO- James Reinders - Director, Chief Software Evangelist. Intel, United States James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including systolic arrays systems WARP and iWarp, and the world's first TeraFLOPS supercomputer (ASCI Red), and the world's first TeraFLOPS microprocessor (Knights Corner), as well as compilers and architecture work for multiple Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James is the author of a book on VTune (Intel Press) and Threading Building Blocks (O'Reilly Media), and a co-author of Structured Parallel Programming (Morgan Kauffman) due out in June 2012. James is currently involved in multiple efforts at Intel to bring parallel programming models to the industry including for the Intel MIC architecture.

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